Merging Unit Maximum Processing Delay (IEC 61869-9)

Short answer

A merging unit takes the signals from the primary, converts them into samples and publishes them in a sampled values frame. Between the instant each sample represents and the instant its frame leaves the port, some time passes. IEC 61869-9, 2016 edition, calls it processing delay.

That time adds to the time the protection takes to detect a fault. That is why the standard obliges the manufacturer to declare the maximum and imposes a cap depending on the application.

What processing delay is

Clause 3.5.902 defines it as the difference between the time encoded in the SmpCnt field of the output message and the instant that message appears at the digital output. Clause 3.5.903 defines the maximum as the largest processing delay under all rated operating conditions.

SmpCnt is a sample counter. It counts from zero at the start of each second, and the instant each sample represents is calculated from it. The frame format is explained in the guide on the 9-2 sampled values message.

The output instant is measured at a precise point of the frame, the message time-stamp point. The standard defines it in figure 907 for the 100BASE-FX physical layer, based on an interpretation of IEEE 1588.

An example from the standard

Figure 906 of the standard shows a merging unit that publishes 4,800 samples per second, one about every 0.2 ms. The sample with SmpCnt equal to 0 encodes the instant xxx.0000 s. It reaches the output at the instant xxx.0009 s. Its processing delay is 0.9 ms.

Since no other sample in the example takes longer, 0.9 ms is also the maximum processing delay of that merging unit.

Limits of Table 901

The manufacturer specifies the maximum delay, and it must be within the limits of Table 901.

The limit is measured at the output of the merging unit. For a protection merging unit at 50 Hz, 2 ms is one tenth of a cycle.

What it does not include

The standard makes clear that the limit does not include the external delays of the process bus network components or congestion. Those delays depend on the application, are critical for system operation and are the responsibility of the integrator, that is, of the engineer who designs the network. They are outside the scope of the standard.

This has a practical consequence. The total time from the primary to the relay is the sum of the merging unit delay, the network delay and the processing delay of the relay itself. A merging unit that meets 2 ms does not by itself guarantee an operating time. Network delays are studied in the guides on the process bus and on sampled values and GOOSE bandwidth.

What happens to the phase angle

With an analog output, the delay affects the estimation of the primary angles. With a digital output, the angle is calculated with the sampling time encoded in the message, not with the moment of reception. The phase error results from the difference between the encoded time and the instant the sample represents at the primary, and is independent of the delay.

The phase error limits in the product standards ensure that the encoded time corresponds to the real instant of the sample. For a relay that compares several merging units, what matters is that all are well synchronized, not that they have the same delay.

The delay does count for something else: it adds to the relay’s fault detection time. For high-performance systems, the standard recommends keeping the maximum delay to a minimum.

In holdover and in free-running mode

Clause 6.902.2 requires the maximum delay to keep meeting the standard, whether the device is synchronized with an external reference or in holdover, that is, running on the time it keeps during a loss of synchronization.

In free-running mode, by definition, the delay cannot be measured, because there is no external reference. It is also not verified separately because of the complexity of precisely measuring high voltage and high current. What is required is that no significant change in delay is observed when going from holdover to free-running mode.

How it is verified

The test is in clause 7.2.902. The processing delay of each frame leaving the digital output is measured. Since the frequency response and phase requirements are already part of accuracy, the encoded time is assumed to correspond to the sampling point at the primary.

Test conditions:

• it lasts at least 1 minute;
• it needs no analog voltage or current signals;
• it uses the same time source that synchronizes the merging unit;
• the uncertainty of the time measurement must be smaller than the difference between the Table 901 limit and the measured maximum;
• if the message carries several samples, it is measured with respect to the first SmpCnt, the oldest.

To see the transition to free-running mode, the test is repeated for 1 s from the instant SmpSynch goes to zero. The maximum measured delay must not change by more than 100 µs from the value of the synchronized test. Equipment with holdover longer than 24 h is exempt and must ensure compliance by design.

What not to do

• Do not take the declared merging unit delay and assume it is the delay of the whole process bus.
• Do not compare merging units of different applications against the same limit.
• Do not use a delay measured with a time source other than the one that synchronizes the device.
• Do not confuse processing delay with the delay of the sampled values network.

Related topics

The delay combines with synchronization, the sampling rate and sample quality. The rated burden and delay of an LPIT complete the calculation. The overview is in merging unit and process bus. To calculate the bandwidth and latency of the process bus, use our free GOOSE/SV address and process bus tool.

When to call us

At Tiza Group we verify the time from the primary to the trip end to end in a digital substation, with the real network. We offer IEC 61850 engineering and end-to-end testing, in Colombia or elsewhere on request. We quote the verification according to the scope of your project.

Related guides

• Merging unit synchronization, holdover and free-running mode
• Merging unit sampling rates: F4800S2I8U0
• Merging unit sample quality: bits and validity
• Merging unit: IEC 61869-9, 9-2LE and testing
• IEC 61850 process bus: SV, GOOSE, timing and bandwidth

References

• IEC 61869-9, Instrument transformers - Part 9: Digital interface for instrument transformers, edition 1.0 of 2016, clauses 3.5.902, 3.5.903, 6.902.2 (Table 901, figures 906 and 907) and 7.2.902.

Frequently asked questions